View X3102V28_1337170.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
X3102
Data Sheet December 22, 2004 FN8246.0
3 Cell Li-Ion Battery Protection and Monitor IC
The X3102 is a protection and monitor IC for use in battery packs consisting of 3 series Lithium-Ion battery cells. The device provides internal over-charge, over-discharge, and overcurrent protection circuitry, internal EEPROM memory, an internal voltage regulator, and internal drive circuitry for external FET devices that control cell charge, discharge, and cell voltage balancing. Over-charge, over-discharge, and overcurrent thresholds reside in an internal EEPROM memory register and are selected independently via software using a 3MHz SPI serial interface. Detection and time-out delays can also be individually varied using external capacitors. Using an internal analog multiplexer, the X3102 allows battery parameters such as cell voltage and current (using a sense resistor) to be monitored externally by a separate microcontroller with A/D converter. Software on this microcontroller implements gas gauge and cell balancing functionality in software. The X3102 contains a current sense amplifier. Selectable gains of 10, 25, 80 and 160 allow an external 10 bit A/D converter to achieve better resolution than a more expensive 14 bit converter. An internal 4kbit EEPROM memory featuring IDLockTM, allows the designer to partition and "lock in" written battery cell/pack data. The X3102 is housed in a 28 Pin TSSOP package.
Features
* Software Selectable Protection Levels and Variable Protect Detection/Release Times * Integrated FET Drive Circuitry * Cell Voltage and Current Monitoring * 0.5% Accurate Voltage Regulator * Integrated 4kbit EEPROM * Flexible Power Management with 1A Sleep Mode * Cell Balancing Control
Benefit
* Optimize protection for chosen cells to allow maximum use of pack capacity. * Reduce component count and cost * Simplify implementation of gas gauge * Accurate voltage and current measurements * Record battery history to optimize gas gauge, track pack failures and monitor system use * Reduce power to extend battery life * Increase battery capacity and improve cycle life battery life
Ordering Information
PART NUMBER X3102V28 VCC LIMITS 6V to 24V TEMP. RANGE (C) -20 to +70 PACKAGE 28 Ld TSSOP
Pinout
X3102 (TSSOP) TOP VIEW
VCELL1 CB1 VCELL2 CB2 VCELL3 CB3 VSS NC VSS VCS1 VCS2 OVT UVT OCT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC RGP RGC RGO UVP/OCP OVP/LMON CS SCK SO SI AS2 AS1 AS0 AO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X3102 Functional Diagram
VCC RGP RGC RGO UVP/OCP OVP/LMON AS0 AS1 Analog MUX AS2 AO
VCELL1 CB1 VCELL2 CB2 VCELL3 CB3 VSS NC Over-charge Over-discharge Protection Sense Circuits Protection Sample Rate Timer
5VDC Regulator Internal Voltage Regulator Power-On reset & Status Register
FET Control Circuitry
4 kbit EEPROM Overcurrent Protection & Current Sense Protection Circuit Timing Control & Configuration Configuration Register Control Register SPI I/F
S0 SCK CS SI
VSS
VCS1
VCS2
OVT
UVT
OCT
Pin Names
PIN 1 SYMBOL VCELL1 DESCRIPTION Battery cell 1 voltage input. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3102 monitors 3 battery cells. Cell balancing FET control output 1. This output is used to switch an external FET in order to perform cell voltage balancing control. This function can be used to adjust an individual cell voltage (e.g., during cell charging). CB1 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. Battery cell 2 voltage. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3102 monitors 3 battery cells. Cell balancing FET control output 2. This output is used to switch an external FET in order to perform cell voltage balancing control. This function can be used to adjust individual cell voltages (e.g., during cell charging). CB2 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. Battery cell 3 voltage. This pin is used to monitor the voltage of each battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3102 monitors 3 battery cells. Cell balancing FET control output 3. This output is used to switch an external FET in order to perform cell voltage balancing control. This function can be used to adjust an individual cell voltage (e.g., during cell charging). CB3 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. Ground. No Connect. Ground. Current sense voltage pin 1. A sense resistor (RSENSE) is connected between VCS1 and VCS2 (Figure 1). RSENSE has a resistance in the order of 20m to 100m, and is used to monitor current flowing through the battery terminals, and protect against overcurrent conditions. The voltage at each end of RSENSE can also be monitored at pin AO. Current sense voltage pin 2. A sense resistor (RSENSE) is connected between VCS1 and VCS2 (Figure 1). RSENSE has a resistance in the order of 20m to 100m, and is used to monitor current flowing through the battery terminals, and protect against overcurrent conditions. The voltage at each end of RSENSE can also be monitored at pin AO. Over-charge detect/release time input. This pin is used to control the delay time (TOV) associated with the detection of an over-charge condition (See section "Over-charge Protection" on page 19). Over-discharge detect/release time input. This pin is used to control the delay times associated with the detection (TUV) and release (TUVR) of an over-discharge (undervoltage) condition (See section "Over-discharge Protection" on page 20). Overcurrent detect/release time input. This pin is used to control the delay times associated with the detection (TOC) and release (TOCR) of an overcurrent condition (See section "Overcurrent Protection" on page 23).
2
CB1
3
VCELL2
4
CB2
5
VCELL3
6
CB3
7 8 9 10
VSS NC VSS VCS1
11
VCS2
12 13 14
OVT UVT OCT
2
FN8246.0 December 22, 2004
X3102 Pin Names (Continued)
PIN 15 SYMBOL AO DESCRIPTION Analog multiplexer output. The analog output pin is used to externally monitor various battery parameter voltages. The voltages which can be monitored at AO (See section "Analog Multiplexer Selection" on page 25) are: - Individual cell voltages - Voltage across the current sense resistor (RSENSE). This voltage is amplified with a gain set by the user in the control register (See section "Current Monitor Function" on page 25.) The analog select pins AS0-AS2 select the desired voltage to be monitored on the AO pin. Analog output select pin 0. These pins select which voltage is to be multiplexed to the output AO (See section "Sleep Control (SLP)" on page 17 and section "Current Monitor Function" on page 25) Analog output select pin 1. These pins select which voltage is to be multiplexed to the output AO (See section "Sleep Control (SLP)" on page 17 and section "Current Monitor Function" on page 25) Analog output select pin 2. These pins select which voltage is to be multiplexed to the output AO (See section "Sleep Control (SLP)" on page 17 and section "Current Monitor Function" on page 25) Serial data input. SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the device are input on this pin. Serial data output. SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. While CS is HIGH, SO will be in a High Impedance state. Note: SI and SO may be tied together to form one line (SI/SO). In this case, all serial data communication with the X3102 is undertaken over one I/O line. This is permitted ONLY if no simultaneous read/write operations occur. Serial data clock input. The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip select input pin. When CS is HIGH, the device is deselected and the SO output pin is at high impedance. CS LOW enables the SPI serial bus.
16 17 18 19 20
AS0 AS1 AS2 SI SO
21
SCK
22 23
CS
OVP/LMON Over-charge Voltage Protection output/Load Monitor output. This one pin performs two functions depending upon the present mode of operation of the X3102. Over-charge Voltage Protection (OVP) This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is possible when OVP/LMON=VSS, and cell charge is prohibited when OVP/LMON=VCC. In this configuration the X3102 turns off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to the application of charging voltage for an extended period of time (See section "Over-charge Protection" on page 19). Load Monitor (LMON) In Overcurrent Protection mode, a small test current (7.5A typ.) is passed out of this pin to sense the load resistance. The measured load resistance determines whether or not the X3102 returns from an overcurrent protection mode (See section "Overcurrent Protection" on page 23).
24
UVP/ OCP
Over-discharge protection output/Overcurrent protection output. Pin UVP/OCP controls the battery cell discharge via an external power FET. This P-channel FET allows cell discharge when UVP/OCP=Vss, and prevents cell discharge when UVP/OCP=Vcc. The X3102 turns the external power FET off when the X3102 detects either: Over-discharge Protection (UVP) In this case, pin 24 is referred to as "Over-discharge (Undervoltage) protection (UVP)" (See section "Over-discharge Protection" on page 20). UVP/OCP turns off the FET to prevent damage to the battery cells by being discharged to excessively low voltages. Overcurrent protection (OCP) In this case, pin 24 is referred to as "Overcurrent protection (OCP)" (See section "Overcurrent Protection" on page 23). UVP/OCP turns off the FET to prevent damage to the battery pack caused by excessive current drain (e.g. as in the case of a surge current resulting from a stalled disk drive).
25
RGO
Voltage regulator output pin. This pin is an input that connects to the collector of an external PNP transistor. The voltage at this pin is the regulated output voltage, but it also provides the feedback voltage for the regulator and the operating voltage for the device. Voltage regulator control pin. This pin connects to the base of an external PNP transistor and controls the transistor turn on. Voltage regulator protection pin. This pin is an input that connects to the emitter of an external PNP transistor and an external current limit resistor and provides a current limit voltage. Power supply. This pin is provides the voltage for FET control, regulator operation, and wake-up circuits.
26 27 28
RGC RGP VCC
3
FN8246.0 December 22, 2004
X3102
Absolute Maximum Ratings
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 to 125C Operating temperature. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to 85C DC output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300C Power supply voltage, VCC . . . . . . . . . . . . . . VSS-0.5 to VSS+27.0V Cell voltage, VCELL. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.75V Terminal voltage, VTERM1 (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1, VCS2, OVT, UVT, OCT, AO) VSS-0.5 to VRGO + 0.5V Terminal voltage, VTERM2 (VCELL1) . . . . .VSS-0.5 to VCC + 1.0V Terminal voltage VTERM3, (all other pins) . .VSS-0.5 to VCC + 0.5V
Recommended Operating Conditions
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20C to +70C Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V to 24V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
SYMBOL ILI ILO
Over the recommended operating conditions, unless otherwise specified TEST CONDITIONS MIN MAX 10 10 -0.3 VRGO x 0.3 UNITS A A V V V V 0.4 VCC - 0.4 0.4 VCC - 4.0 V V V V
PARAMETER Input leakage current (SCK, SI, CS, ASO, AS1, AS2) Output leakage current (SO)
VIL Input LOW voltage (SCK, SI, CS, AS0, AS1, AS2) (Note 1) VIH Input HIGH voltage (SCK, SI, CS, AS0, AS1, AS2) (Note 1) VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 NOTE: 1. VIL min. and VIH max. are for reference only and are not 100% tested. Output LOW voltage (SO) Output HIGH voltage (SO) Output LOW voltage (UVP/OCP, OVP/LMON, CB1-CB4) Output HIGH voltage (UVP/OCP, OVP/LMON, CB1-CB4) Output LOW voltage (RGC) Output HIGH voltage (RGC) IOL = 1.0mA IOH = -0.4mA IOL = 100A IOH = -20A IOL = 2mA, RGP = VCC, RGO = 5V IOH = -20A, RGP = VCC - 4V, RGO = 5V
VRGO x 0.7 VRGO + 0.3 0.4 VRGO - 0.8
Operating Specifications Over the recommended operating conditions unless otherwise specified
SYMBOL VRGO DESCRIPTION 5V regulated voltage CONDITION On power up or at wake-up After self-tuning (@ 10mA VRGO current; 25C) After self-tuning (@ 10mA VRGO current; 0-50C) (Note 5) After self-tuning (@ 50mA VRGO current) (Note 5) ILMT 5VDC voltage regulator current limit (Note 3) Icc1 Icc2 Icc3 Icc4 Icc5 VCC supply current (1) VCC supply current (2) VCC supply current (3) VCC supply current (4) VCC supply current (5) RLMT = 10 Normal operation during nonvolatile EEPROM write During EEPROM read SCK = 3.3MHz Sleep mode Monitor mode AN2, AN1, AN0 not equal to 0 365 MIN 4.5 4.97 4.95 4.90 250 85 1.3 0.9 250 2.5 1.2 1 600 4.99 TYP (Note 2) MAX 5.5 5.01 5.02 5.00 V mA A mA mA A A UNIT V
4
FN8246.0 December 22, 2004
X3102
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
SYMBOL DESCRIPTION CONDITION MIN 4.10 0C to 50C 4.15 4.15 0C to 50C VOV = 4.30V (VOV1, VOV0 = 1,0) 0C to 50C VOV = 4.35V (VOV1, VOV0 = 1,1) 0C to 50C VOVR TOV Cell over-charge protection mode release voltage threshold Cell over-charge detection time COV = 0.1F VUV = 2.25V (VUV1, VUV0 = 0,0) VUV = 2.35V (VUV1, VUV0 = 0,1) VUV = 2.45V (VUV1, VUV0 = 1,0) VUV = 2.55V (VUV1, VUV0 = 1,1) VUVR TUV Cell over-discharge protection mode release threshold Cell over-discharge detection time CUV = 0.1F CUV = 200pF TUVR Cell over-discharge release time CUV = 0.1F CUV = 200pF VOC Overcurrent mode detection (Note 4) voltage (Default in Boldface) VOC = 0.075V (VOC1, VOC0 = 0,0) 0.050 0C to 50C 0.060 VOC = 0.100V (VOC1, VOC0 = 0,1) 0.075 0C to 50C 0.085 VOC = 0.125V (VOC1, VOC0 = 1,0) 0C to 50C VOC = 0.150V (VOC1, VOC0 = 1,1) 0.100 0.110 0.125 0C to 50C 0.135 TOC Overcurrent mode detection time COC = 0.001F COC = 200pF TOCR Overcurrent mode release time COC = 0.001F COC = 200pF ROCR Load resistance overcurrent mode release condition Releases when OVP/LMON pin > 2.5V 10 2 10 2 250 2.15 2.25 2.35 2.45 VUV + 0.6 1 2 7 100 0.100 0.090 0.125 0.115 0.150 0.140 0.175 0.165 ms ms ms ms k V V V 4.20 4.2 4.25 4.25 4.30 VOV 0.20 1 2.35 2.45 2.55 2.65 TYP (Note 2) MAX 4.275 4.25 4.325 4.30 4.375 4.35 4.425 4.40 V V V V V V V s V V V V V s ms ms s V UNIT V
VOV Cell over-charge protection mode voltage VOV = 4.20V (VOV1, VOV0 = 0,0) (Note 4) threshold (Default in Boldface) VOV = 4.25V (VOV1, VOV0 = 0,1)
VUV Cell over-discharge protection mode (Note 4) (SLEEP) threshold. (Default in Boldface)
5
FN8246.0 December 22, 2004
X3102
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
SYMBOL VCE DESCRIPTION Cell charge threshold voltage CONDITION VCE = 0.5V (VCE1, VCE0 = 0,0) VCE = 0.8V (VCE1, VCE0 = 0,1) VCE = 1.1V (VCE1, VCE0 = 1,0) VCE = 1.4V (Vce1, VCE0 = 1,1) VSLR VSLP NOTES: 2. Typical at 25C. 3. See Figure 10 on page 21. 4. The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register. 5. For reference only, this parameter is not 100% tested. X3102 wake-up voltage (For Vcc above this voltage, the device wakes up) (See Wake-up test circuit) 0C to 50C MIN 0.4 0.7 1 1.3 8.5 7.5 TYP (Note 2) 0.5 0.8 1.1 1.4 9.5 8.8 MAX 0.6 0.9 1.2 1.5 11.2 10.5 UNIT V V V V V V
X3102 sleep voltage (For Vcc above this (See Sleep test circuit) 0C to 50C voltage, the device cannot go to sleep)
Test Circuits
VCC VCC
VCC RGP VCELL1 VCELL2 VCELL3 1V VCELL4 RGC RGO VRGO 1V
VCC RGP VCELL1 VCELL2 1V VCELL3 VCELL4 RGC RGO VRGO
VSS Increase Vcc until VRGO turns on
VSS Decrease Vcc until VRGO turns off
WAKE-UP TEST CIRCUIT
SLEEP TEST CIRCUIT
Power-Up Timing
SYMBOL tPUR (Note 6) tPUW1 (Note 6) tPUW2 (Note 6) PARAMETER Power-up to SPI read operation (RDSTAT, EEREAD STAT) Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR) Power-up to SPI write operation (WCNTR - bits 10 and 11) MIN MAX TOC + 2ms TOC + 2ms TOV + 200ms or TUV + 200ms (Note 7) UNIT ms ms ms
NOTES: 6. tPUR, tPUW1 and tPUW2 are the delays required from the time VCC is stable until a read or write can be initiated. These parameters are not 100% tested. 7. Whichever is longer.
6
FN8246.0 December 22, 2004
X3102 Capacitance TA = +25C, f = 1MHz, VRGO = 5V
SYMBOL COUT (Note 8) Output capacitance (SO) CIN (Note 8) NOTE: 8. This parameter is not 100% tested. Input capacitance (SCK, SI, CS) PARAMETER CONDITIONS VOUT = 0V VIN = 0V MAX 8 6 UNITS pF pF
Equivalent A.C. Load Circuit
5V 2061 SO 3025 30pF
A.C. Test Conditions
Input pulse levels Input rise and fall times Input and output timing level 0.5 - 4.5V 10ns 2.5V
A.C. Characteristics (Over the recommended operating conditions, unless otherwise specified.)
Serial Input Timing
SYMBOL fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI (Note 9) tFI (Note 9) tCS tWC (Note 10) NOTES: 9. This parameter is not 100% tested. 10. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Data in rise time Data in fall time CS deselect time Write cycle time 100 5 PARAMETER MIN 0 300 150 150 130 130 20 20 2 2 MAX 3.3 UNITS MHz ns ns ns ns ns ns ns s s ns ms
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
SO
7
FN8246.0 December 22, 2004
X3102
Serial Output Timing
SYMBOL fSCK tDIS tV tHO tRO (Note 11) tFO (Note 11) NOTE: 11. This parameter is not 100% tested. Clock Frequency Output Disable Time Output Valid from Clock LOW Output Hold Time Output Rise Time Output Fall Time 0 50 50 PARAMETER MIN 0 MAX 3.3 150 130 UNITS MHz ns ns ns ns ns
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB In
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
8
FN8246.0 December 22, 2004
X3102 Analog Output Response Time
SYMBOL PARAMETER AO Output Stabilization Time (Voltage Source Change) AO Output Stabilization Time (Current Sense Gain Change) Control Outputs Response Time (UVP/OCP, OVP/MON, CB4, CB3, CB2, CB1, RGC) MIN TYP MAX UNITS
tVSC tCSGO tCO
1.0 1.0 1.0
ms ms s
Change in Voltage Source
AS2:AS0
AO
tVSC
tVSC
Change in Current Sense Gain Amplification and Control Bits
CS
SCK
DI Control Reg
OVPC Bit10
CSG1 Bit9
CSG0 Bit8
SLP Bit7
0 Bit6
0 Bit5
x
AO Current Sense Gain Change
Old Gain tCSGO New Gain
UVP/OCP OVP/LMON CB3:CB1 RGC Control Outputs
On
Off tCO
9
FN8246.0 December 22, 2004
X3102 Typical Operating Characteristics
150 450
125 CURRENT (A) 400 CURRENT (A)
100
350
75
50
-20
25 TEMPERATURE
80
300
-20
25 TEMPERATURE
80
FIGURE 1. NORMAL OPERATING CURRENT
FIGURE 2. MONITOR MODE CURRENT
4.40 REGULATOR VOLTAGE (V) 4.35 VOLTAGE (V) 4.30 4.25 4.20 4.15 -25
5.020 5.000 4.980 4.960 4.940 4.920 4.900 4.880 VCC = 10.8V to 16V RLIM = 15 (ILIM = 200mA) 1 10 LOAD (mA) 50 100 -25C 75C 25C
4.35V 4.3V 4.25V 4.2V 25 TEMPERATURE (C) 75
FIGURE 3. OVER CHARGE TRIP VOLTAGE (TYPICAL)
FIGURE 4. VOLTAGE REGULATOR OUTPUT (TYPICAL)
2.60 2.55 2.50 VOLTAGE (V) 2.45 2.40 2.35 2.30 2.25 -25
2.55V REGULATED VOLTAGE
5.020 5.000 1mA LOAD 4.980 4.960 4.940 100mA LOAD 4.920 4.900 4.880 -25 VCC = 10.8V to 16V RLIM = 15 (ILIM = 200mA) 25 TEMPERATURE (C) 75 10mA LOAD 50mA LOAD
2.45V
2.35V
2.25V 25 TEMPERATURE (C) 75
FIGURE 5. OVER DISCHARGE TRIP VOLTAGE (TYPICAL)
FIGURE 6. VOLTAGE REGULATOR OUTPUT (TYPICAL)
10
FN8246.0 December 22, 2004
X3102 Principles of Operation
The X3102 provides two distinct levels of functionality and battery cell protection: First, in Normal mode, the device periodically checks each cell for an over-charge and over-discharge state, while continuously watching for a pack overcurrent condition. A protection mode violation results from an over-charge, overdischarge, or overcurrent state. The thresholds for these states are selected by the user through software. When one of these conditions occur, a Discharge FET or a Charge FET or both FETs are turned off to protect the battery pack. In an over-discharge condition, the X3102 device goes into a low power sleep mode to conserve battery power. During sleep, the voltage regulator turns off, removing power from the microcontroller to further reduce pack current. Second, in Monitor mode, a microcontroller with A/D converter measures battery cell voltage and pack current via pin AO and the X3102 on-board MUX. The user can thus implement protection, charge/discharge, cell balancing or gas gauge software algorithms to suit the specific application and characteristics of the cells used. While monitoring these voltages, all protection circuits are on continuously. In a typical application, the microcontroller is also programmed to provide an SMBus interface along with the Smart Battery System interface protocols. These additions allow an X3102 based module to adhere to the latest industry battery pack standards. The operation of the voltage regulator is described in section "Voltage Regulator" on page 26. This regulator provides a 5VDC0.5% output. The capacitor (C1) connected from RGO to ground provides some noise filtering on the RGO output. The recommended value is 0.1F or less. The value chosen must allow VRGO to decay to 0.1V in 170ms or less when the X3102 enters the sleep mode. If the decay is slower than this, a resistor (R1) can be placed in parallel with the capacitor. During an initial turn-on period (TPUR + TOC), VRGO has a stable, regulated output in the range of 5VDC 10% (See Figure 8). The selection of the microcontroller should take this into consideration. At the end of this turn on period, the X3102 "self-tunes" the output of the voltage regulator to 5V0.5%. As such, VRGO can be used as a reference voltage for the A/D converter in the microcontroller. Repeated power up operations, consistently re-apply the same "tuned" value for VRGO. Figure 1 shows a battery pack temperature sensor implemented as a simple resistive voltage divider, utilizing a thermistor (RT) and resistor (RT'). The voltage VT can be fed to the A/D input of a microcontroller and used to measure and monitor the temperature of the battery cells. RT' should be chosen with consideration of the dynamic resistance range of RT as well as the input voltage range of the microcontroller A/D input. An output of the microcontroller can be used to turn on the thermistor divider to allow periodic turn-on of the sensor. This reduces power consumption since the resistor string is not always drawing current. Diode D3 is included to facilitate load monitoring in an overcurrent protection mode (See section "Overcurrent Protection" on page 23), while preventing the flow of current into pin OVP/LMON during normal operation. The N-Channel transistor turns off this function during the sleep mode. Resistor RPU is connected across the gate and drain of the charge FET (Q2). The discharge FET Q1 is turned off by the X3102, and hence the voltage at pin OVP/LMON will be (at maximum) equal to the voltage of the battery terminal, minus one forward biased diode voltage drop (VP+-VD7). Since the drain of Q2 is connected to a higher potential (VP+) a pull-up resistor (RPU) in the order of 1M should be used to ensure that the charge FET is completely turned OFF when OVP/LMON = VCC.
Typical Application Circuit
The X3102 has been designed to operate correctly when used as connected in the Typical Application Circuit (See Figure 7). The power MOSFET's Q1 and Q2 are referred to as the "Discharge FET" and "Charge FET," respectively. Since these FETs are p-channel devices, they will be ON when the gates are at VSS, and OFF when the gates are at VCC. As their names imply, the discharge FET is used to control cell discharge, while the charge FET is used to control cell charge. Diode D1 allows the battery cells to receive charge even if the Discharge FET is OFF, while diode D2 allows the cells to discharge even if the charge FET is OFF. D1 and D2 are integral to the Power FETs. It should be noted that the cells can neither charge nor discharge if both the charge FET and discharge FET are OFF. Power to the X3102 is applied to pin VCC via diodes D6 and D7. These diodes allow the device to be powered by the Li-Ion battery cells in normal operating conditions, and allow the device to be powered by an external source (such as a charger) via pin P+ when the battery cells are being charged. These diodes should have sufficient current and voltage ratings to handle both cases of battery cell charge and discharge.
11
FN8246.0 December 22, 2004
D6 BAT54
D7 BAT54 D1 D2
Charge FET P+
Q1 Discharge FET
Q2
RPU
1M
ILMON D3 Transistor Recommendations Q1, Q2 = Si4435 Q3 = 2N3906 Q4 - Q10 = 2N7002
Q10 ILMT 3 or 4 Li-Ion cells B+ VCC 1 RCB Q6 100 RCB Q7 5 100 RCB Q8 0.01F 6 CB3 7 VSS 8 NC AO VSS 9 BVCS1 10 VCS2 11 COV RSENSE OVT UVT OCT 14 VT RT 12 CUV 13 COC 15 0.01F 4 CB2 VCELL3 100 0.01F 2 3 VCELL2 CS SCK 22 21 20 19 CB1 RGP RGC RGO UVP/ OCP OVP/ LMON . 1F 28 RLMT 27 26 25 24 23 Q3 VRGO C1 0.1F R1 1M (Optional)
12
VCELL1
C, ASIC VCC A/D Ref GP I/O RT' GP I/O Reset CPOR Set High after power up to enable SMBus and LMON
Choose R1 and C1 such that VRGO goes to 0.1V (or less) in 170ms (or less) when entering the Sleep Mode (at 25C).
RPOR
X3102
X3102
SO SI
GP I/O 18
Q5
Q4
SMBCLK
AS2 AS1 AS0
100 100 SMBDATA
17 16
A/D Input A/D Input
FETs Q4 and Q5 are needed only if external pull-ups on the SMBus lines cause voltage to appear at the uC Vcc pin during sleep mode.
P-
FN8246.0 December 22, 2004
FIGURE 7. TYPICAL APPLICATION CIRCUIT
X3102
The capacitors on the VCELL1 to VCELL4 inputs are used in a first order low pass filter configuration, at the battery cell voltage monitoring inputs (VCELL1-VCELL4) of the X3102. This filter is used to block any unwanted interference signals from being inadvertently injected into the monitor inputs. These interference signals may result from: * Transients created at battery contacts when the battery pack is being connected/disconnected from the charger or the host. * Electrostatic discharge (ESD) from something/someone touching the battery contacts. * Unfiltered noise that exists in the host device. * RF signals which are induced into the battery pack from the surrounding environment. Such interference can cause the X3102 to operate in an unpredictable manner, or in extreme cases, damage the device. As a guide, the capacitor should be in the order of 0.01F and the resistor, should be in the order of 10K. The capacitors should be of the ceramic type. In order to minimize interference, PCB tracks should be made as short and as wide as possible to reduce their impedance. The battery cells should also be placed as close to the X3102 monitor inputs as possible. Resistors RCB and the associated n-channel MOSFET's (Q6-Q9) are used for battery cell voltage balancing. The X3102 provides internal drive circuitry which allows the user to switch FETs Q6-Q9 ON or OFF via the microcontroller and SPI port (See section "Cell Voltage Balance Control (CBC1-CBC3)" on page 17). When any of the these FETs are switched ON, a current, limited by resistor RCB, flows across the particular battery cell. In doing so, the user can control the voltage across each individual battery cell. This is important when using Li-Ion battery cells since imbalances in cell voltages can, in time, greatly reduce the usable capacity of the battery pack. Cell voltage balancing may be implemented in various ways, but is usually performed towards the end of cell charging ("Top-of-charge method"). Values for RCB will vary according to the specific application. The internal 4kbit EEPROM memory can be used to store the cell characteristics for implementing such functions as gas gauging, battery pack history, charge/discharge cycles, and minimum/maximum conditions. Battery pack manufacturing data as well as serial number information can also be stored in the EEPROM array. An SPI serial bus provides the communication link to the EEPROM. A current sense resistor (RSENSE) is used to measure and monitor the current flowing into/out of the battery terminals, and is used to protect the pack from overcurrent conditions (See section "Overcurrent Protection" on page 23). RSENSE is also used to externally monitor current via a microcontroller (See section "Current Monitor Function" on page 25). FETs Q4 and Q5 may be required on general purpose I/Os of the microcontroller that connect outside of the package. In some cases, without FETs, pull-up resistors external to the pack force a voltage on the VCC pin of the microcontroller during a pack sleep condition. This voltage can affect the proper tuned voltage of the X3102 regulator. These FETs should be turned-on by the microcontroller. (See Figure 1.)
Power On Sequence
Initial connection of the Li-Ion cells in the battery pack will not normally power up the battery pack. Instead, the X3102 enters and remains in the SLEEP mode. To exit the SLEEP mode, after the initial power up sequence, or following any other SLEEP MODE, a minimum of 8.5V is applied to the VCC pin, as would be the case during a battery charge condition. (See Figure 8.) When VSLR is applied to VCC, the analog select pins (AS2- AS0) and the SPI communication pins (CS, CLK, SI, SO) must be low, so the X3102 powers up correctly into the normal operating mode. This can be done by using a poweron reset circuit. When entering the normal operating mode, either from initial power up or following the SLEEP MODE, all bits in the control register are zero. With UVPC and OVPC bits at zero, the charge and discharge FETs are off. The microcontroller must turn these on to activate the pack. The microcontroller would typically check the voltage and current levels prior to turning on the FETs via the SPI port. The software should prevent turning on the FETs throughout an initial measurement/calibration period. The duration of this period is TOV + 200ms or TUV + 200ms, whichever is longer.
13
FN8246.0 December 22, 2004
X3102
TPUR
VCC
VSLR
0V
5V10% (Stable and Repeatable) VRGO Tuned to 5V0.5% 5V VRGO 0V 2ms (Typ.)
Voltage Regulator Output Status (Internal Signal) VRGS TOC 1 Overcurrent Detection Status (Internal Signal) OCDS
1 0
1 = X3102 in overcurrent Protection Mode 0 = X3102 NOT in overcurrent Protection Mode 0 1 1 = X3102 in overcurrent Protection Mode OR VRGO Not Yet Tuned 0 = X3102 NOT in overcurrent Protection Mode AND VRGO Tuned 0 TOV+200ms 1
Status Register Bit 0 VRGS+OCDS
Status Register Bit 2 (SWCEN = 0) CCES+OVDS 1 = VCELL < VCE OR X3102 in Over-charge Protection Mode 0 = VCELL > VCE OR X3102 NOT in Over-charge Protection Mode 1 Status Register Bit 2 (SWCEN = 1) OVDS 1 = X3102 in Over-charge Protection Mode 0 = X3102 NOT in Over-charge Protection Mode
0
0
From Microcontroller
AS2_AS0 TOV+200ms OR TUV+200ms (whichever is longer) SPI PORT
Any Read or Write Operation, except turnon of FETs can start here.
Charge, Discharge FETs can be turned on here.
FIGURE 8. POWER UP TIMING (INITIAL POWER UP OR AFTER SLEEP MODE)
14
FN8246.0 December 22, 2004
X3102 Configuration Register
The X3102 can be configured for specific user requirements using the Configuration Register.
TABLE 1. CONFIGURATION REGISTER FUNCTIONALITY BIT(s) 0-5 6 7 8-9 10-11 12-13 14-15 NAME - SWCEN CELLN VCE1-VCE0 VOC1-VOC0 VUV1-VUV0 VOV1-VOV0 (don't care) Switch Cell Charge Enable threshold function ON/OFF Set the number of Li-Ion battery cells used (3 or 4) Select Cell Charge Enable threshold Select overcurrent threshold Select over-discharge (under voltage) threshold Select over-charge voltage threshold FUNCTION
Over-Discharge Settings
VUV1 and VUV0 control the cell over-discharge (under voltage threshold) level. See section "Over-discharge Protection" on page 20.
TABLE 5. OVER-DISCHARGE THRESHOLD SELECTION CONFIGURATION REGISTER BITS VUV1 0 0 1 1 VUV0 0 1 0 1 OPERATION VUV = 2.25V (default) VUV = 2.35V VUV = 2.45V VUV = 2.55V
Overcurrent Settings
VOC1 and VOC0 control the pack overcurrent level. See section "Overcurrent Protection" on page 23.
TABLE 6. OVERCURRENT THRESHOLD VOLTAGE SELECTION. CONFIGURATION REGISTER BITS VOC1 0 VOC0 0 1 0 1 OPERATION VOC = 0.075V (Default) VOC = 0.100V VOC = 0.125V VOC = 0.150V
TABLE 2. CONFIGURATION REGISTER - UPPER BYTE 15 VOV1 14 VOV0 13 VUV1 12 VUV0 11 VOC1 10 VOC0 9 VCE1 8 VCE0
Default = 03H TABLE 3. CONFIGURATION REGISTER - LOWER BYTE 7 CELLN Default = 40H 6 SWCEN 5 x 4 x 3 x 2 x 1 x 0 x
0 1 1
Cell Charge Enable Settings Over-Charge Voltage Settings
VOV1 and VOV0 control the cell over-charge level. See section "Over-charge Protection" on page 19.
TABLE 4. OVER-CHARGE VOLTAGE THRESHOLD SELECTION CONFIGURATION REGISTER BITS VOV1 0 0 1 1 VOV0 0 1 0 1 OPERATION VOV = 4.20V (Default) VOV = 4.25V VOV = 4.30V VOV = 4.35V
VCE1, VCE0 and SWCEN control the pack charge enable function. SWCEN enables or disables a circuit that prevents charging if the cells are at too low a voltage. VCE1 and VCE0 select the voltage that is recognized as too low. See section "Sleep Mode" on page 20.
TABLE 7. CELL CHARGE ENABLE FUNCTION CONFIGURATION REGISTER BIT SWCEN 0 1 OPERATION Charge enable function: ON Charge enable function: OFF
TABLE 8. CELL CHARGING THRESHOLD VOLTAGE SELECTION. CONFIGURATION REGISTER BITS VCE1 0 0 1 1 VCE0 0 1 0 1 OPERATION VCE = 0.5V VCE = 0.80V VCE = 1.10V VCE = 1.40V (Default)
15
FN8246.0 December 22, 2004
X3102
Cell Number Selection
The X3102 is designed to operate with three (3) Li-Ion battery cells. The CELLN bit of the configuration register (Table 9) sets the number of cells recognized. For the X3102, the value for CELLN should always be zero.
TABLE 9. SELECTION OF NUMBER OF BATTERY CELLS CONFIGURATION REGISTER BIT CELLN 1 0 Not used 3 Li-Ion battery cells
NO Store (New Value) in Shadow EEPROM YES Power Up Data Recalled from Shadow EEPROM to SRAM Configuration Register (SRAM=Old Value) WCFIG (New Value)
OPERATION
Configuration Register (Sram=New Value)
The configuration register consists of 16 bits of NOVRAM memory (Table 2, Table 3). This memory features a highspeed static RAM (SRAM) overlaid bit-for-bit with nonvolatile "Shadow" EEPROM. An automatic array recall operation reloads the contents of the shadow EEPROM into the SRAM configuration register upon power-up (Figure 9).
Configuration Register (SRAM) Upper Byte Lower Byte
WREN Power Down Power Up Data Recalled from Shadow EEPROM to SRAM Configuration Register (SRAM=old value) Power Down Power Up Data Recalled from Shadow EEPROM to SRAM Configuration Register (SRAM=New Value) EEWRITE Write to 4kbit EEPROM Write Enable
Recall
Recall Shadow EEPROM
FIGURE 9. POWER UP OF CONFIGURATION REGISTER
The configuration register is designed for unlimited write operations to SRAM, and a minimum of 1,000,000 store operations to the EEPROM. Data retention is specified to be greater than 100 years. It should be noted that the bits of the shadow EEPROM are for the dedicated use of the configuration register, and are NOT part of the general purpose 4kbit EEPROM array. The WCFIG command writes to the configuration register, see Table 30 and section "X3102 SPI Serial Communication" on page 27. After writing to this register using a WCFIG instruction, data will be stored only in the SRAM of the configuration register. In order to store data in shadow EEPROM, a WREN instruction, followed by a EEWRITE to any address of the 4kbit EEPROM memory array must occur, See Figure 10. This sequence initiates an internal nonvolatile write cycle which permits data to be stored in the shadow EEPROM cells. It must be noted that even though a EEWRITE is made to the general purpose 4kbit EEPROM array, the value and address to which it is written, is unimportant. If this procedure is not followed, the configuration register will power up to the last previously stored values following a power down sequence.
FIGURE 10. WRITING TO CONFIGURATION REGISTER
Control Register
The Control Register is realized as two bytes of volatile RAM (Table 10, Table 11). This register is written using the WCNTR instruction, see Table 30 and section "X3102 SPI Serial Communication" on page 27.
TABLE 10. CONTROL REGISTER - UPPER BYTE 14 x 14 CBC3 13 CBC2 12 CBC1 11 UVPC 10 OVPC 9 CSG1 8 CSG0
TABLE 11. CONTROL REGISTER - LOWER BYTE 7 SLP 6 0 5 0 4 x 3 x 2 x 1 x 0 x
Since the control register is volatile, data will be lost following a power down and power up sequence. The default value of the control register on initial power up or when exiting the SLEEP MODE is 00h (for both upper and lower
16
FN8246.0 December 22, 2004
X3102
bytes respectively). The functions that can be manipulated by the Control Register are shown in Table 12.
TABLE 12. CONTROL REGISTER FUNCTIONALITY BIT(S) 0-4 5, 6 7 8,9 10 11 12 13 14 15 NAME - 0, 0 SLP CSG1, CSG0 OVPC UVPC CBC1 CBC2 CBC3 - (don't care) Reserved--write 0 to these locations. Select sleep mode. Select current sense voltage gain OVP control: switch pin OVP = VCC/VSS UVP control: switch pin UVP = VCC/VSS CB1 control: switch pin CB1 = VCC/VSS CB2 control: switch pin CB2 = VCC/VSS CB3 control: switch pin CB3 = VCC/VSS (don't care) FUNCTION
OVP/LMON and UVP/OCP can be controlled by using the WCNTR Instruction to set bits OVPC and UVPC in the Control register (See page 17).
TABLE 15. UVP/OVP CONTROL CONTROL REGISTER BITS OVPC 1 0 x x UVPC x x 1 0 OPERATION Pin OVP = VSS (FET ON) Pin OVP = VCC (FET OFF) Pin UVP = VSS (FET ON) Pin UVP = VCC (FET OFF)
It is possible to set/change the values of OVPC and UVPC during a protection mode. A change in the state of the pins OVP/LMON and UVP/OCP, however, will not take place until the device has returned from the protection mode.
Sleep Control (SLP)
Setting the SLP bit to `1' forces the X3102 into the sleep mode, if VCC < VSLP. See section "Sleep Mode" on page 20.
TABLE 13. SLEEP MODE SELECTION CONTROL REGISTER BITS SLP 0 1 OPERATION Normal operation mode Device enters Sleep mode
Cell Voltage Balance Control (CBC1-CBC3)
This function can be used to adjust individual battery cell voltage during charging. Pins CB1-CB3 are used to control external power switching devices. Cell voltage balancing is achieved via the SPI port.
TABLE 16. CB1-CB3 CONTROL Control Register Bits CBC3 x x x x 1 0 x x CBC2 x x 1 0 x x x x CBC1 1 0 x x x x x x Operation Set CB1 = VCC (ON) Set CB1 = VSS (OFF) Set CB2 = VCC (ON) Set CB2 = VSS (OFF) Set CB3 = VCC (ON) Set CB3 = VSS (OFF) Set CB4 = VCC (ON) Set CB4 = VSS (OFF)
Current Sense Gain (CSG1, CSG0)
These bits set the gain of the current sense amplifier. These are x10, x25, x80 and x160. For more detail, see section "Current Monitor Function" on page 25.
TABLE 14. CURRENT SENSE GAIN CONTROL CONTROL REGISTER BITS CSG1 0 0 1 1 CSG0 0 1 0 1 OPERATION Set current sense gain=x10 Set current sense gain=x25 Set current sense gain=x80 Set current sense gain=x160
CB1-CB3 can be controlled by using the WCNTR Instruction to set bits CBC1-CBC3 in the control register (Table 16).
Status Register
The status of the X3102 can be verified by using the RDSTAT command to read the contents of the Status Register (Table 17).
TABLE 17. STATUS REGISTER 7 0 6 0 5 0 4 0 3 0 2 CCES + OVDS 1 UVDS 0 VRGS + OCDS
Charge/Discharge Control (OVPC, UVPC)
The OVPC and UVPC bits allow control of cell charge and discharge externally, via the SPI port. These bits control the OVP/LMON and UVP/OCP pins, which in turn control the external power FETs. Using P-channel power FETs ensures that the FET is on when the pin voltage is low (Vss), and off when the pin voltage is high (Vcc).
17
FN8246.0 December 22, 2004
X3102
The function of each bit in the status register is shown in Table 18. Bit 0 of the status register (VRGS + OCDS) actually indicates the status of two conditions of the X3102. Voltage Regulator Status (VRGS) is an internally generated signal which indicates that the output of the Voltage Regulator (VRGO) has reached an output of 5VDC 0.5%. In this case, the voltage regulator is said to be "tuned". Before the signal VRGS goes low (i.e. before the voltage regulator is tuned), the voltage at the output of the regulator is nominally 5VDC 10% (See section "Voltage Regulator" on page 26.) Overcurrent Detection Status (OCDS) is another internally generated signal which indicates whether or not the X3102 is in overcurrent protection mode. Signals VRGS and OCDS are logically OR'ed together (VRGS+OCDS) and written to bit 0 of the status register (See Table 18, Table 17 and Figure 8). Bit 1 of the status register simply indicates whether or not the X3102 is in over-discharge protection mode. Bit 2 of the status register (CCES + OVDS) indicates the status of two conditions of the X3102. Cell Charge Enable Status (CCES) is an internally generated signal which indicates the status of any cell voltage (VCELL) with respect to the Cell Charge Enable Voltage (VCE). Over-charge Voltage Detection Status (OVDS) is an internally generated signal which indicates whether or not the X3102 is in overcharge protection mode. When the cell charge enable function is switched ON (configuration bit SWCEN = 0), the signals CCES and OVDS are logically OR'ed (CCES + OVDS) and written to bit 2 of the status register. If the cell charge enable function is switched OFF (configuration bit SWCEN = 1), then bit 2 of the status register effectively only represents information about the over-charge status (OVDS) of the X3102 (See Table 18, Table 17 and Figure 8).
TABLE 18. STATUS REGISTER FUNCTIONALITY BIT(S) 0 NAME VRGS + OCDS DESCRIPTION Voltage regulator status + Overcurrent detection status Over-discharge detection status Cell charge enable status + Over-charge detection status CASE STATUS 1 0 1 0 SWCEN = 0 (Note) 1 0 SWCEN = 1 (Note) 3-7 - 1 0 0 INTERPRETATION VRGO not yet tuned (VRGO = 5V 10%) OR X3102 in overcurrent protection mode. VRGO tuned (VRGO = 5V 0.5%) AND X3102 NOT in overcurrent protection mode. X3102 in over-discharge protection mode X3102 NOT in over-discharge protection mode VCELL < VCE OR X3102 in over-charge protection mode VCELL > VCE AND X3102 NOT in over-charge protection mode X3102 in over-charge protection mode X3102 NOT in over-charge protection mode Not used (always return zero)
1
UVDS
2
CCES + OVDS
NOTE: This bit is set in the configuration register.
18
FN8246.0 December 22, 2004
X3102 X3102 Internal Protection Functions
The X3102 provides periodic monitoring (See section "Periodic Protection Monitoring" on page 19) for over-charge and over-discharge states and continuous monitoring for an overcurrent state. It has automatic shutdown when a protection mode is encountered, as well as automatic return after the device is released from a protection mode. When sampling voltages through the analog port (Monitor Mode), over-charge and over-discharge protection monitoring is also performed on a continuous basis. Voltage thresholds for each of these protection modes (VOV, VUV, and VOC respectively) can be individually selected via software and stored in an internal non-volatile register. This feature allows the user to avoid the restrictions of mask programmed voltage thresholds, and is especially useful during prototype/evaluation design stages or when cells with slightly different characteristics are used in an existing design. Delay times for the detection of, and release from protection modes (TOV, TUV/TUVR, and TOC/TOCR respectively) can be individually varied by setting the values of external capacitors connected to pins OVT, UVT, OCT.
Over-charge Protection
The X3102 monitors the voltage on each battery cell (VCELL). If for any cell, VCELL > VOV for a time exceeding TOV, then the Charge FET will be switched OFF (OVP/LMON=VCC). The device has now entered Overcharge protection mode (Figure 11). The status of the discharge FET (via pin UVP) will remain unaffected. While in over-charge protection mode, it is possible to change the state of the OVPC bit in the control register such that OVP/LMON=Vss (Charge FET=ON). Although the OVPC bit in the control register can be changed, the change will not be seen at pin OVP until the X3102 returns from over-charge protection mode. The over-charge detection delay TOV, is varied using a capacitor (COV) connected between pin OVT and GND. A typical delay time is shown in Table 10. The delay TOV that results from a particular capacitance COV, can be approximated by the following linear equation: TOV (s) 10 x COV (F).
TABLE 19. TYPICAL OVER-CHARGE DETECTION TIME Symbol TOV COV 0.1F Delay 1.0s (Typ)
Periodic Protection Monitoring
In normal operation, the analog select pins are set such that AS2 = L, AS1 = L, AS0 = L. In this mode the X3102 conserves power by sampling the cells for over or overdischarge conditions. In this state over-charge and over-discharge protection circuitry are usually off, but are periodically switched on by the internal Protection Sample Rate Timer (PSRT). The overcharge and over-discharge protection circuitry is on for approximately 2ms in each 125ms period. Overcurrent monitoring is continuous. In monitor mode (See page 25) over-charge and over-discharge monitoring is also continuous.
The device further continues to monitor the battery cell voltages, and is released from over-charge protection mode when VCELL< VOVR, for all cells. When the X3102 is released from over-charge protection mode, the charge FET is automatically switched ON (OVP/LMON=VSS). When the device returns from over-charge protection mode, the status of the discharge FET (pin UVP/OCP) remains unaffected. The value of VOV can be selected from the values shown in Table 4 by setting bits VOV1, VOV0. These bits are set by using the WCFIG instruction to write to the configuration register.
Normal Operation Mode
Over-charge Protection Mode
Normal Operation Mode
VOV VOVR VCELL TOV VCC OVP/LMON VSS
Event
0 1 2 3
FIGURE 11. OVER-CHARGE PROTECTION MODE-EVENT DIAGRAM
19
FN8246.0 December 22, 2004
X3102
TABLE 20. OVER-CHARGE PROTECTION MODE-EVENT DIAGRAM DESCRIPTION EVENT [0,1) * Discharge FET is ON (UVP/OCP=VSS). * Charge FET is ON (OVP/LMON=VSS), and hence battery cells are permitted to receive charge. * All cell voltages (VCELL - VCELL4) are below the over-charge voltage threshold (VOV). * The device is in normal operation mode (i.e. not in a protection mode). [1] * The voltage of one or more of the battery cells (VCELL), exceeds VOV. * The internal over-charge detection delay timer begins counting down. * The device is still in normal operation mode (1,2) [2] The internal over-charge detection delay timer continues counting for TOV seconds. The internal over-charge detection delay timer times out AND VCELL still exceeds VOV. * Therefore, the internal over-charge sense circuitry switches the charge FET OFF (OVP/LMON=Vcc). * The device has now entered over-charge protection mode. (2,3) * While in over-charge protection mode: * The battery cells are permitted to discharge via the discharge FET, and diode D2 across the charge FET * The X3102 monitors the voltages VCELL1 - VCELL4 to determine whether or not they have all fallen below the "Return from overcharge threshold" (VOVR). * (It is possible to change the status of UVP/OCP or OVP/LMON using the control register) [3] * All cell voltages fall below VOVR--The device is now in normal operation mode. * The X3102 automatically switches charge FET = ON (OVP/LMON = Vss) * The status of the discharge FET remains unaffected. * Charging of the battery cells can now resume. EVENT DESCRIPTION
Over-discharge Protection
If VCELL < VUV, for a time exceeding TUV, the cells are said to be in a over-discharge state (Figure 12). In this instance, the X3102 automatically switches the discharge FET OFF (UVP/OCP=Vcc), and then enter sleep mode. The over-discharge (undervoltage) value, VUV, can be selected from the values shown in Table 5 by setting bits VUV1, VUV0 in the configuration register. These bits are set using the WCFIG command. Once in the sleep mode, the following steps must occur before the X3102 allows the battery cells to discharge: * The X3102 must wake from sleep mode (See section "Voltage Regulator" on page 26). * The charge FET must be switched ON by the microcontroller (OVP/LMON=VSS), via the control register (See section "CONTROL REGISTER FUNCTIONALITY" on page 17). * All battery cells must satisfy the condition: VCELL > VUVR for a time exceeding TUVR. * The discharge FET must be switched ON by the microcontroller (UVP/OCP=VSS), via the control register (See section "CONTROL REGISTER FUNCTIONALITY" on page 17) The times TUV/TUVR are varied using a capacitor (CUV) connected between pin UVT and GND (Table 13). The delay
TUV that results from a particular capacitance CUV, can be approximated by the following linear equation: TUV (s) 10 x CUV (F) TUVR (ms) 70 x CUV (F)
TABLE 21. TYPICAL OVER-DISCHARGE DELAY TIMES SYMBOL TUV TUVR DESCRIPTION Over-discharge detection delay Over-discharge release time CUV 0.1F 0.1F DELAY 1.0s (Typ) 7ms (Typ)
Sleep Mode
The X3102 can enter sleep mode in two ways: i) The device enters the over-discharge protection mode.
ii) The user sends the device into sleep mode using the control register. A sleep mode can be induced by the user, by setting the SLP bit in the control register (Table 13) using the WCNTR Instruction. In sleep mode, power to all internal circuitry is switched off, minimizing the current drawn by the device to 1A (max). In this state, the discharge FET and the charge FET are switched OFF (OVP/LMON=VCC and UVP/OCP=VCC), and the 5VDC regulated output (VRGO) is 0V. Control of
20
FN8246.0 December 22, 2004
X3102
UVP/OCP and OVP/LMON via bits UVPC and OVPC in the control register is also prohibited. The device returns from sleep mode when VCC VSLR. (e.g. when the battery terminals are connected to a battery charger). In this case, the X3102 restores the 5VDC regulated output (section "Voltage Regulator" on page 26), and communication via the SPI port resumes. If the Cell Charge Enable function is enabled when VCC rises above VSLR, the X3102 internally verifies that the individual battery cell voltages (VCELL) are larger than the cell charge enable voltage (VCE) before allowing the FETs to be turned on. The value of VCE is selected by using the WCFIG command to set bits VCE1-VCE0 in the configuration register. cell then both the Charge FET and the discharge FET are OFF (OVP/LMON = VCC and UVP/OCP = VCC). Thus both charge and discharge of the battery cells via terminals P+ / P- is prohibited (See Note).
NOTE: In this case, charging of the battery may resume ONLY if the cell charge enable function is switched OFF by setting bit SWCEN=1 in the configuration register (See Above, "CONFIGURATION REGISTER FUNCTIONALITY" on page 15).
The cell charging threshold function can be switched ON or OFF by the user, by setting bit SWCEN in the configuration register (Table 7) using the WCFIG command. In the case that this cell charge enable function is switched OFF, then VCE is effectively set to 0V. The X3102 cannot enter sleep mode (automatically or manually, by setting the SLP bit) if VCC VSLR. This is to ensure that the device does not go into a sleep mode while the battery cells are at a high voltage (e.g. during cell charging).
Only if the condition "VCELL > VCE" is satisfied can the state of charge and discharge FETs be changed via the
control register. Otherwise, if VCELL < VCE for any battery
VCC Cell Charge Prohibited if SWCEN=0 AND VCELL < VCE VCELL 0.7V VUV TUVR
VSLR
VUVR
VCE
TUV VCC UVP/OCP Over-discharge Protection Mode Note 3 VSS
The Longer of TOV+200ms OR TUV+200ms VCC OVP/LMON RGO Sleep Mode Notes 1, 2 VSS 5V 0V Event 0 1 2 3 4 5
NOTES: 1. If SWEN=0 and VCELL < VCE, then OVP/LMON stays high and charging is prohibited.
2. OVP/LMON stays high until the microcontroller writes a "1" to the OVPC bit in the control register. This sets the signal low, which turns on the charge FET. It cannot be turned on prior to this time. 3. UVP/OCP stays high until the microcontroller writes a "1" to the UVPC bit in the control register. This sets the signal low, which turns on the discharge FET. The FET cannot be turned on prior to this time.
FIGURE 12. OVER-DISCHARGE PROTECTION MODE-EVENT DIAGRAM
21
FN8246.0 December 22, 2004
X3102
TABLE 22. OVER-DISCHARGE PROTECTION MODE--EVENT DIAGRAM DESCRIPTION EVENT [0,1) * Charge FET is ON (OVP/LMON = VSS) * Discharge FET is ON (UVP/OCP = VSS), and hence battery cells are permitted to discharge. * All cell voltages (VCELL1-VCELL4) are above the Over-discharge threshold voltage (VUV). * The device is in normal operation mode (i.e. not in a protection mode). [1] * The voltage of one or more of the battery cells (VCELL), falls below VUV. * The internal over-discharge detection delay timer begins counting down. * The device is still in normal operation mode (1,2) [2] * The internal over-discharge detection delay timer continues counting for TUV seconds. * The internal over-discharge detection delay timer times out, AND VCELL is still below VUV. * The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc). * The charge FET is switched OFF (OVP/LMON = VCC). * The device has now entered over-discharge protection mode. * At the same time, the device enters sleep mode (See section "Voltage Regulator" on page 26). (2,3) * While device is in sleep (in over-discharge protection) mode: * The power to ALL internal circuits is switched OFF limiting power consumption to less than 1A. * The output of the 5VDC voltage regulator (RGO) is 0V. * Access to the X3102 via the SPI port is NOT possible. [3] * Return from sleep mode (but still in over-discharge protection mode): * Vcc rises above the "Return from Sleep mode threshold Voltage" (VSLR)--This would normally occur in the case that the battery pack was connected to a charger. The X3102 is now powered via P+/P-, and not the battery pack cells. * Power is returned to ALL internal circuitry * 5VDC output is returned to the regulator output (RGO). * Access is enabled to the X3102 via the SPI port. * The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control register, although it will have no effect at this time). (3,4) If the cell charge enable function is * The X3102 initiates a reset operation that takes the longer of TOV+200ms or TUV+200ms to complete. Do not write to the FET control bits during this time. switched ON AND VCELL > VCE * The charge FET is switched On (OVP/LMON = Vss) by the microcontroller by writing a "1" to OR the OVPC bit in the control register. Charge enable function is * The battery cells now receive charge via the charge FET and diode D1 across the discharge switched OFF FET (which is OFF). * The X3102 monitors the VCELL voltage to determine whether or not it has risen above VUVR. If the cell charge enable function is * Charge/discharge of the battery cells via P+ is no longer permitted (Charge FET and discharge switched ON FET are held OFF). AND * (Charging may re-commence only when the Cell Charge Enable function is switched OFF VCELL < VCE See Sections: "Configuration Register" page 4, and "Sleep mode" page 17.) [4] * The voltage of all of the battery cells (VCELL), have risen above VUVR. * The internal Over-discharge release timer begins counting down. * The X3102 is still in over-discharge protection mode. (4,5) * The internal over-discharge release timer continues counting for tUVR seconds. * The X3102 should be in monitor mode (AS2:AS0 not all low) for recovery time based on tUVR. Otherwise recovery is based on two successive samples about 120ms apart. [5] * The internal over-discharge release timer times out, AND VCELL is still above VUVR. * The device returns from over-discharge protection mode, and is now in normal operation mode. * The Charger voltage can now drop below VSLR and the X3102 will not go back to sleep. * The discharge FET is can now be switched ON (UVP/OCP = VSS) by the microcontroller by writing a "1" to the UVPC bit of the control register. * The status of the charge FET remains unaffected (ON) * The battery cells continue to receive charge via the charge FET and discharge FET (both ON). EVENT DESCRIPTION
22
FN8246.0 December 22, 2004
X3102
Overcurrent Protection
In addition to monitoring the battery cell voltages, the X3102 continually monitors the voltage VCS21 (VCS2-VCS1) across the current sense resistor (RSENSE). If VCS21 > VOC for a time exceeding TOC, then the device enters overcurrent protection mode (Figure 7). In this mode, the X3102 automatically switches the discharge FET OFF (UVP/OCP = Vcc) and hence prevent current from flowing through the terminals P+ and P-. TOCR (ms) 10,000 x COC (F)
TABLE 23. TYPICAL OVERCURRENT DELAY TIMES Symbol TOC TOCR Description Overcurrent detection delay Overcurrent release time COC 0.001F 0.001F Delay 10ms (Typ) 10ms (Typ)
Q2
ILMON D1 VRGO Q10
P+
The value of VOC can be selected from the values shown in Table 6, by setting bits VOC1, VOC0 in the configuration register using the WCFIG command. Note: If the Charge FET is turned off, due to an overcharge condition or by direct command from the microcontroller, the cells are not in an undervoltage condition and the pack has a load, then excessive current may flow through Q10 and diode D1. To eliminate this effect, the gate of Q10 can be turned off by the microcontroller.
OVP/LMON X3102 FET Control Circuitry
ROCR (Load)
VSS
VCS1
VCS2 P-
RSENSE
FIGURE 13. OVERCURRENT PROTECTION
The 5VDC voltage regulator output (VRGO) is always active during an overcurrent protection mode. Once the device enters overcurrent protection mode, the X3102 begin a load monitor state. In the load monitor state, a small current (ILMON = 7.5A typ.) is passed out of pin OVP/ LMON in order to determine the load resistance. The load resistance is the impedance seen looking out of pin OVP/ LMON, between terminal P+ and pin VSS (See Figure 13.) If the load resistance > ROCR (ILMON = 0A) for a time exceeding TOCR, then the X3102 is released from overcurrent protection mode. The discharge FET is then automatically switched ON (UVP/OCP = Vss) by the X3102, unless the status of UVP/OCP has been changed in control register (by manipulating bit UVPC) during the overcurrent protection mode. TOC/TOCR are varied using a capacitor (COC) connected between pin OCT and VSS. A list of typical delay times is shown in Table 23. Note that the value COC should be larger than 1nF. The delay TOC and TOCR that results from a particular capacitance COC can be approximated by the following equations: TOC (ms) 10,000 x COC (F) 23
FN8246.0 December 22, 2004
X3102
Normal Operation Mode B+ P+ Overcurrent Protection Mode Normal Operation Mode
P+ = (RLOAD+RSENSE) x ILMON
VOC VCS2 TOC TOCR
Voc VSS
VCC UVP/OCP VSS
Event 0 1 2 3 4
FIGURE 14. OVERCURRENT PROTECTION MODE - EVENT DIAGRAM
TABLE 24. OVERCURRENT PROTECTION MODE-EVENT DIAGRAM DESCRIPTION EVENT [0,1) EVENT DESCRIPTION * Discharge FET is ON (OCP = Vss). Battery cells are permitted to discharge. * VCS21 (VCS2-VCS1) is less than the overcurrent threshold voltage (VOC). * The device is in normal operation mode (i.e. not in a protection mode). * * * * Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 14.). The positive battery terminal voltage (P+) falls, and VCS21 exceeds VOC. The internal overcurrent detection delay timer begins counting down. The device is still in Normal Operation Mode
[1]
(1,2) [2]
The internal Overcurrent detection delay timer continues counting for TOC seconds. * The internal overcurrent detection delay timer times out, AND VCS21 is still above VOC. * The internal overcurrent sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc). * The device now begins a load monitor state by passing a small test current (ILMON = 7.5A) out of pin OVP/LMON. This senses if an overcurrent condition (i.e. if the load resistance < ROCR) still exists across P+/P-. * The device has now entered overcurrent protection mode. * It is possible to change the status of UVPC and OVPC in the control register, although the status of pins UVP/OCP and OVP/LMON will not change until the device has returned from overcurrent protection mode. * The X3102 now continuously monitors the load resistance to detect whether or not an overcurrent condition is still present across the battery terminals P+/P-. * * * * * * The device detects the load resistance has risen above ROCR. Voltages P+ and VCS21 return to their normal levels. The test current from pin OVP/LMON is stopped (ILMON = 0A) The device has now returned from the load monitor state The internal overcurrent release time timer begins counting down. Device is still in overcurrent protection mode.
(2,3) [3]
(3,4) [4]
The internal overcurrent release timer continues counting for TOCR seconds. * The internal overcurrent release timer times out, and VCS21 is still below VOC. * The device returns from overcurrent protection mode, and is now in normal operation mode. * The discharge FET is automatically switched ON (UVP/OCP = Vss) - unless the status of UVPC has been changed in the control register during the overcurrent protection mode. * The status of the charge FET remains unaffected. * Discharge of the battery cells is once again possible.
24
FN8246.0 December 22, 2004
X3102 Monitor Mode
Analog Multiplexer Selection
The X3102 can be used to externally monitor individual battery cell voltages, and battery current. Each quantity can be monitored at the analog output pin (AO), and is selected using the analog select (AS0-AS2) pins (Table 25). Also, see Figure 15.
TABLE 25. AO SELECTION MAP AS2 L L L L H H H H NOTES: 1. This is the normal state of the X3102. While in this state Overcharge and Over-discharge Protection conditions are periodically monitored (See "Periodic Protection Monitoring" on page 19.) 2. VCS1, VCS2 are read at AO with respect to a DC bias voltage of 2.5V (See section "Current Monitor Function" on page 25). AS1 L L H H L L H H AS0 L H L H L H L H VSS(1) VCELL1-VCELL2 (VCELL12) VCELL2-VCELL3 (VCELL23) VCELL3-VCELL4 (VCELL34) VCELL4-Vss (VCELL4) VCS1-VCS2 (VCS12)(2) VCS2-VCS1 (VCS21)(2) VSS
VCS1 VCS2 RSENSE Cross-Bar Switch Overcurrent Protection X3102 PR1 Config Register Gain Setting SPI I/F Voltage Level Shifters Cell 1 Voltage Cell 2 Voltage Cell 3 Voltage Cell 4 Voltage
Analog MUX
AS0 AS1 AS2 AO
2.5V R2 + R1 R2 OP1
AO OUTPUT
S0 SCL CS SI
CSG1 CSG0
FIGURE 15. MONITOR CIRCUIT
Current Monitor Function
The voltages monitored at pins VCS1 and VCS2 can be used to calculate current flowing through the battery terminals, using an off-board microcontroller with an A/D. Since the value of the sense resistor (RSENSE) is small (typically in the order of tens of m), and since the resolution of various A/D converters may vary, the voltage across RSENSE (VCS1 and VCS2) is amplified internally with a gain of between 10 and 160, and output to pin AO (Figure 15).
The internal gain of the X3102 current sense voltage amplifier can be selected by using the WCNTR Instruction to set bits CSG1 and CSG0 in the control register (Table 14). The CSG1 and CSG0 bits select one of four input resistors to Op Amp OP1. The feedback resistors remain constant. This ratio of input to feedback resistors determines the gain. Putting external resistors in series with the inputs reduces the gain of the amplifier. VCS1 and VCS2 are read at AO with respect to a DC bias voltage of 2.5V. Therefore, the voltage range of VCS12 and VCS21 changes depending upon the direction of current flow (i.e. battery cells are in Charge or Discharge - Table 21).
TABLE 26. AO VOLTAGE RANGE FOR VCS12 AND VCS21 AO VCS12 VCS12 VCS21 VCS21 CELL STATE Charge Discharge Charge Discharge AO VOLTAGE RANGE 2.5V AO 5.0V 0V AO 2.5V 0V AO 2.5V 2.5V AO 5.0V
By calculating the difference of VCS12 and VCS21 the offset voltage of the internal op-amp circuitry is cancelled. This allows for the accurate calculation of current flow into and out of the battery cells. Pack current is calculated using the following formula:
( VCS 12 - VCS 21 ) Pack Current = --------------------------------------------------------------------------------------------------------( 2 ) ( gain setting )(current sense resistor)
25
FN8246.0 December 22, 2004
X3102 Voltage Regulator
The X3102 is able to supply peripheral devices with a regulated 5VDC0.5% output at pin RGO. The voltage regulator should be configured externally as shown in Figure 16. The non-inverting input of OP1 is fed with a high precision 5VDC supply. The voltage at the output of the voltage regulator (VRGO) is compared to this 5V reference via the inverting input of OP1. The output of OP1 in turn drives the regulator pnp transistor (Q1). The negative feedback at the regulator output maintains the voltage at 5VDC 0.5% (including ripple) despite changes in load, and differences in regulator transistors. When power is applied to pin VCC of the X3102, VRGO is regulated to 5VDC10% for a nominal time of TOC+2ms. During this time period, VRGO is "tuned" to attain a final value of 5VDC 0.5% (Figure 8). The maximum current that can flow from the voltage regulator (ILMT) is controlled by the current limiting resistor (RLMT) connected between RGP and VCC. When the voltage across VCC and RGP reaches a nominal 2.5V (i.e. the threshold voltage for the FET), Q2 switches ON, shorting VCC to the base of Q1. Since the base voltage of Q1 is now higher than the emitter voltage, Q1 switches OFF, and hence the supply current goes to zero. Typical values for RLMT and ILMT are shown in Table 27. In order to protect the voltage regulator circuitry from damage in case of a short-circuit, RLMT 10 should always be used.
TABLE 27. TYPICAL VALUES FOR RLMT AND ILMT RLMT 10 25 50 VOLTAGE REGULATOR CURRENT LIMIT (ILMT) 250mA 50% (Typical) 100mA 50% (Typical) 50mA 50% (Typical)
To Internal Voltage Regulating Circuitry X3102 Tuning Q2 RGP ILMT VCC
Un-Regulated Voltage Input RLMT
5VDC Precision Voltage Reference
+ _ OP1
RGC
Q1
Regulated RGO 5VDC Output 0.1 F VRGO
FIGURE 16. VOLTAGE REGULATOR OPERATION
4KBit EEPROM Memory
The X3102 contains a CMOS 4k-bit serial EEPROM, internally organized as 512 x 8 bits. This memory is accessible via the SPI port, and features the IDLock function. The 4kbit EEPROM array can be accessed by the SPI port at any time, even during a protection mode, except during sleep mode. After power is applied to VCC of the X3102, EEREAD and EEWRITE Instructions can be executed only after times tPUR (power up to read time) and tPUW (power up to write time) respectively. IDLock is a programmable locking mechanism which allows the user to lock data in different portions of the EEPROM memory space, ranging from as little as one page to as much as 1/2 of the total array. This is useful for storing information such as battery pack serial number, manufacturing codes, battery cell chemistry data, or cell characteristics.
When choosing the value of RLMT, the drive limitations of the PNP transistor used should also be taken into consideration. The transistor should have a gain of at least 100 to support an output current of 250mA.
EEPROM Write Enable Latch
The X3102 contains an EEPROM "Write Enable" latch. This latch must be SET before a write to EEPROM operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 17). This latch is automatically reset upon a power-up condition and after the completion of a byte or page write cycle.
IDLock Memory
Intersil's IDLock memory provides a flexible mechanism to store and lock battery cell/pack information. There are seven distinct IDLock memory areas within the array which vary in size from one page to as much as half of the entire array.
26
FN8246.0 December 22, 2004
X3102
Prior to any attempt to perform an IDLock operation, the WREN instruction must first be issued. This instruction sets the "Write Enable" latch and allows the part to respond to an IDLock sequence. The EEPROM memory may then be IDLocked by writing the SET IDL instruction (Table 30 and Figure 25), followed by the IDLock protection byte.
TABLE 28. IDLock PARTITION BYTE DEFINITION IDLock PROTECTION BYTES 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 EEPROM MEMORY ADDRESS IDLocked None 000h-07Fh 080h-0FFh 100h-17Fh 180h-1FFh 000h-0FFh 000h-00Fh 1F0h-1FFh
memory array that are IDLocked can be read but not written until IDLock is removed or changed.
TABLE 29. IDLock REGISTER 7 0 6 0 5 0 4 0 3 0 2 IDL2 1 IDL1 0 IDL0
NOTE: Bits [7:3] specified to be "0's".
X3102 SPI Serial Communication
The X3102 is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. This interface uses four signals, CS, SCK, SI and SO. The signal CS when low, enables communications with the device. The SI pin carries the input signal and SO provides the output signal. SCK clocks data in or out. The X3102 operates in SPI mode 0 which requires SCK to be normally low when not transferring data. It also specifies that the rising edge of SCK clocks data into the device, while the falling edge of SCK clocks data out. This SPI port is used to set the various internal registers, write to the EEPROM array, and select various device functions. The X3102 contains an 8-bit instruction register. It is accessed by clocking data into the SI input. CS must be LOW during the entire operation. Table 30 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock, and then start it again to resume operations where left off.
The IDLock protection byte contains the IDLock bits IDL2IDL0, which defines the particular partition to be locked (Table 28). The rest of the bits [7:3] are unused and must be written as zeroes. Bringing CS HIGH after the two byte IDLock instruction initiates a nonvolatile write to the status register. Writing more than one byte to the status register will overwrite the previously written IDLock byte. Once an IDLock instruction has been completed, that IDLock setup is held in a nonvolatile IDLock Register (Table 29) until the next IDLock instruction is issued. The sections of the
TABLE 30. INSTRUCTION SET INSTRUCTION NAME WREN WRDI EEWRITE EEREAD STAT EEREAD WCFIG WCNTR RDSTAT SET IDL INSTRUCTION FORMAT* 0000 0110 0000 0100 0000 0010 0000 0101 0000 0011 0000 1001 0000 1010 0000 1011 0000 0001 DESCRIPTION Set the write enable latch (write enable operation) (Figure 17) Reset the write enable latch (write disable operation) (Figure 17) Write command followed by address/data (4kbit EEPROM) (Figure 18, Figure 19) Reads IDLock settings & status of EEPROM EEWRITE instruction (Figure 20) Read operation followed by address (for 4kbit EEPROM) (Figure 21) Write to configuration register followed by two bytes of data (Figure 10, Figure 22). Data stored in SRAM only and will power-up to previous settings (Figure 9) Write to control register, followed by two bytes of data (Figure 23) Read contents of status register (Figure 24) Set EEPROM ID lock partition followed by partition byte (Figure 25)
*Instructions have the MSB in leftmost position and are transferred MSB first.
27
FN8246.0 December 22, 2004
X3102
Write Enable/Write Disable (WREN/WRDI)
Any write to a nonvolatile array or register, requires the WREN command be sent prior to the write command. This command sets an internal latch allowing the write operation to proceed. The WRDI command resets the internal latch if the system decides to abort a write operation. See Figure 17.
CS
the data to be written. Only the last 9 bits of the address are used and bits [15:9] are specified to be zeroes. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 16 bytes of data to the X3102. The only restriction is the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been previously written. For a byte or page write operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed. Refer to Figure 18 and Figure 19 for detailed illustration of the write sequences and time frames in which CS going HIGH are valid.
0 SCK
1
2
3
4
5
6
7
Instruction (1 Byte) SI
WREN
SO
High Impedance
WRDI
EEPROM Read Status Operation (EEREAD STAT)
If there is not a nonvolatile write in progress, the EEREAD STAT instruction returns the IDLock byte from the IDLock register which contains the IDLock bits IDL2-IDL0 (Table 29). The IDLock bits define the IDLock condition (Table 28). The other bits are reserved and will return `0' when read. If a nonvolatile write to the EEPROM (i.e. EEWRITE instruction) is in progress, the EEREAD STAT returns a HIGH on SO. When the nonvolatile write cycle in the EEPROM is completed, the status register data is read out. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (See Figure 20).
FIGURE 17. EEPROM WRITE ENABLE LATCH (WREN/WRDI) OPERATION SEQUENCE
EEPROM Write Sequence (EEWRITE)
Prior to any attempt to write data into the EEPROM of the X3102, the "Write Enable" latch must first be set by issuing the WREN instruction (See Table 30 and Figure 17). CS is first taken LOW. Then the WREN instruction is clocked into the X3102. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user issues the EEWRITE instruction, followed by the 16 bit address and
CS
0 SCK
1
2
3
4
5
6
7
8
9
20
21
22
23
24
25
26
27
28
29
30
31
EEWRITE Instruction (1 Byte) SI 15
Byte Address (2 Byte) 14 3 2 1 0 7 6 5
Data Byte 4 3 2 1 0
High Impedance SO
FIGURE 18. EEPROM BYTE WRITE (EEWRITE) OPERATION SEQUENCE
28
FN8246.0 December 22, 2004
X3102
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
31
EEWRITE Instruction SI 15 14
Byte Address (2 Byte) 13 3 2 1 0 7 6 5
Data Byte 1 4 3 2 1 0
CS 145 146 147 148 149 150 1 151 0
32 SCK
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 5
Data Byte 3 4 3 2 1 0 6 5
Data Byte 16 4 3 2
FIGURE 19. EEPROM PAGE WRITE (EEWRITE) OPERATION SEQUENCE
CS
0 SCK
1
2
3
4
5
6
7 ...
EEREAD STAT Instruction SI Nonvolatile EEWRITE in Progress I D L 2 I D L 1 I D L 0 ...
SO SO High During Nonvolatile EEWRITE Cycle
...
SO=Status Reg Bit When No Nonvolatile EEWRITE Cycle
FIGURE 20. EEPROM READ STATUS (EEREAD STAT) OPERATION SEQUENCE
EEPROM Read Sequence (EEREAD)
When reading from the X3102 EEPROM memory, CS is first pulled LOW to select the device. The 8-bit EEREAD instruction is transmitted to the X3102, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specified to be zeroes). After the EEREAD opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (01FFh), the address counter rolls over to address 0000h, allowing the read cycle 29
to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the EEPROM Read (EEREAD) operation sequence illustrated in Figure 21.
Write Configuration Register (WCFIG)
The Write Configuration Register (WCFIG) instruction updates the static part of the Configuration Register. These new values take effect immediately, for example writing a new Over-discharge voltage limit. However, to make these changes permanent, so they remain if the cell voltages are removed, an EEWRITE operation to the EEPROM array is required following the WCFIG command. This command is shown in Figure 22.
FN8246.0 December 22, 2004
X3102
CS
0 SCK
1
2
3
4
5
6
7
8
9
20
21
22
23
24
25
26
27
28
29
30
31
EEREAD Instruction (1 Byte) SI 15
Byte Address (2 Byte) 14 3 2 1 0
Data Out
High Impedance SO
7
6
5
4
3
2
1
0
FIGURE 21. EEPROM (EEREAD) READ OPERATION SEQUENCE
CS
0 SCK
1
2
3
4
5
6
7
8
9
20
21
22
23
WCFIG Instruction SI (1 BYTE) High Impedance SO 15
Configuration Register Data 14 (2 BYTE) 3 2 1 0
FIGURE 22. WRITE CONFIGURATION REGISTER (WCFIG) OPERATION SEQUENCE
CS
0 SCK
1
2
3
4
5
6
7
8
9
18
19
20
21
22
23
WCNTR Instruction SI (1 Byte) High Impedance SO Control Bits 15 14
Control Register Data 5 (2 Byte) 4 3 2 1 0
Old Control Bits
New Control Bits
FIGURE 23. WRITE CONTROL REGISTER (WCNTR) OPERATION SEQUENCE
Write Control Register (WCNTRL)
The Write Control Register (WCNTRL) instruction updates the contents of the volatile Control Register. This command sets the status of the FET control pins, the cell balancing outputs, the current sense gain and external entry to the 30
sleep mode. Since this instruction controls a volatile register, no other commands are required and there is no delay time needed after the instruction, before subsequent commands. The operation of the WCNTRL command is shown in Figure 23.
FN8246.0 December 22, 2004
X3102
Read Status Register (RDSTAT)
The Read Status Register (RDSTAT) command returns the status of the X3102. The Status Register contains three bits that indicate whether the voltage regulator is stabilized, and if there are any protection failure conditions. The operation of the RDSTAT instruction is shown in Figure 24.
Set ID Lock (SET IDL)
The contents of the EEPROM memory array in the X3102 can be locked in one of eight configurations using the SET ID lock command. When a section of the EEPROM array is locked, the contents cannot be changed, even when a valid write operation attempts a write to that area. The SET IDL command operation is shown in Figure 25.
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDSTAT Instruction SI (1 Byte) High Impedance Status Register Output
SO
2
1
0
FIGURE 24. READ STATUS REGISTER (RDSTAT) OPERATION SEQUENCE
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Set IDL Instruction
IDLock Byte I D L 2 I D L 1 I D L 0
SI
High Impedance SO
FIGURE 25. EEPROM IDLock (SET IDL) OPERATION SEQUENCE
31
FN8246.0 December 22, 2004
X3102
28-Lead Plastic, TSSOP, Package Code V28
.026 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.377 (9.60) .385 (9.80)
.047 (1.20) .0075 (.19) .0118 (.30)
.002 (.06) .005 (.15)
.010 (.25) Gage Plane 0 - 8 .020 (.50) .030 (.75) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) See Detail "A" All Measurements are Typical Seating Plane (1.78) (4.16) (7.72)
NOTE: All dimensions in inches (in parentheses in millimeters)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 32
FN8246.0 December 22, 2004

▲Up To Search▲

Price & Availability of X3102V28

	To Download X3102V28 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .